1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a front-end unit having an interface function and a back-end unit including a memory core are integrated on separate semiconductor chips.
2. Description of Related Art
Memory capacities required for semiconductor memory devices such as a DRAM (Dynamic Random Access Memory) are increasing year by year. To satisfy this requirement, a memory device called “multi chip package” having a plurality of memory chips stacked has been proposed in recent years. However, ordinary memory chips that can operate independently by themselves are used in the multi chip package. The ordinary memory chip includes a so-called front end unit that establishes interface to outside (a memory controller, for example). Accordingly, a chip area that a memory core can be formed in each memory chip is limited by existence of the front end unit. It is therefore difficult to greatly increase a memory capacity of one memory chip.
Additionally, although the front end unit is a logic circuit, transistors including the front end unit are fabricated at the same time as transistors including a back end unit constituing a memory core. Therefore, it is difficult to speed-up the transistors of the front end unit.
To solve these problems, a method that enables to constitute one semiconductor memory device by integrating a front end unit and a back end unit on separate chips, respectively, and stacking these chips has been proposed (see Japanese Patent Application Laid-open No. 2007-157266). According to this method, the chip areas that the memory core can be formed become larger in the plural core chips, and therefore the memory capacity of one core chip can be increased. On the other hand, an interface chip that has the front end unit can be fabricated by a process different from the memory core, which allows the logic circuits to be formed by a high-speed transistor. Furthermore, because the plural core chips can be allocated to one interface chip, a semiconductor memory device with a quite large capacity and a high speed operation can be provided.
However, this type of semiconductor memory may be recognized as one memory chip by an exterenal controller. Accordingly, when plural core chips are allocated to one interface chip, how to perform an individual access to each core chip becomes an issue. That is, in the ordinary multi chip package, each memory chip can be individually selected by using a chip select terminal (/CS) provided on each memory chip. In contrast, in the semiconductor memory device described above, a chip select terminal is provided on the interface chip. Therefore, each core chip cannot be individually selected by using a chip selection signal.
As a method for solving this problem, Japanese Patent Application Laid-open No. 2007-157266 realizes individual selection of each core chip by allocating chip addresses to the respective core chips and commonly supplying a chip selection address to the respective core chips from an interface chip.
Meanwhile, a plurality of operation modes may be prepared for semiconductor devices such as the DRAM. One of the operation modes is selected at the manufacturing stages. This is because it is not efficient to separately design and manufacture semiconductor devices with respect to each operation mode. The same holds true for stacked semiconductor devices. It is considered desirable that plural operation modes are prepared and one of the operation modes is selected at the manufacturing stages.
However, because selection of each core chip in the stacked semiconductor device is performed based on a chip selection address, bits of an address and the like to be used as the chip selection address vary according to the operation modes. Therefore, a circuit that changes the bits of an address and the like to be used as the chip selection address according to the operation modes is required. When such a circuit is provided in each core chip, the circuit scale is increased.